Comparative study of phase lead compensator based in-loop filtering method in single-phase PLL

Paper

Gautam, Samir, Lu, Yuezhu, Xiao, Weidong, Lu, Dylan Dah-Chuan and Golsorkhi, Mohammad S.. 2020. "Comparative study of phase lead compensator based in-loop filtering method in single-phase PLL." IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society. Singapore 18 - 21 Oct 2020 United States. IEEE (Institute of Electrical and Electronics Engineers). https://doi.org/10.1109/IECON43393.2020.9255138
Paper/Presentation Title

Comparative study of phase lead compensator based in-loop filtering method in single-phase PLL

Presentation TypePaper
AuthorsGautam, Samir, Lu, Yuezhu, Xiao, Weidong, Lu, Dylan Dah-Chuan and Golsorkhi, Mohammad S.
Journal or Proceedings TitleProceedings of IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society
Journal Citationpp. 4947-4954
Number of Pages8
Year2020
PublisherIEEE (Institute of Electrical and Electronics Engineers)
Place of PublicationUnited States
ISBN9781728154145
Digital Object Identifier (DOI)https://doi.org/10.1109/IECON43393.2020.9255138
Web Address (URL) of Paperhttps://ieeexplore.ieee.org/abstract/document/9255138
Web Address (URL) of Conference Proceedingshttps://ieeexplore.ieee.org/xpl/conhome/9254213/proceeding
Conference/EventIECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society
Event Details
IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society
Delivery
Online
Event Date
18 to end of 21 Oct 2020
Event Location
Singapore
Abstract

Accurate estimation of grid voltage parameters (phase, frequency and amplitude) from Phase Locked Loop (PLL) is a challenging task under distorted and abnormal grid conditions. To equip PLLs in such scenarios, additional filters can be appended inside the control loop. The improvement in steady-state accuracy then comes in exchange of reduced control bandwidth because of phase delay introduced by filters. To boost the dynamic response, a preferred solution is cascading phase lead compensator (PLC) (with filters), while maintaining the disturbance rejection capability. This paper assesses performance of two types of PLCs (standard and digital) which are designed to minimize the phase delay of in-loop filters employed in PLL. These two approaches are compared by evaluating their dynamic response, steady-state accuracy and implementation complexity. The paper also provides design guidelines for both types of PLC along with its effect on controller design. The discussions presented are validated via simulation and experimental results.

KeywordsSingle Phase System; Phase Locked Loops; Phase Lead Compensator; Filters(MAF, DSC)
Contains Sensitive ContentDoes not contain sensitive content
ANZSRC Field of Research 20204008. Electrical engineering
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Byline AffiliationsUniversity of Sydney
University of Technology Sydney
Isfahan University of Technology, Iran
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