An FPGA-based fast two-symbol processing architecture for JPEG 2000 arithmetic coding
Paper
Paper/Presentation Title | An FPGA-based fast two-symbol processing architecture for JPEG 2000 arithmetic coding |
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Presentation Type | Paper |
Authors | Ramesh Kumar, Nandini (Author), Xiang, Wei (Author) and Wang, Yafeng (Author) |
Journal or Proceedings Title | Proceedings of the 35th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2010) |
ERA Conference ID | 50073 |
Number of Pages | 4 |
Year | 2010 |
Place of Publication | United States |
ISBN | 9781424442966 |
Digital Object Identifier (DOI) | https://doi.org/10.1109/ICASSP.2010.5495418 |
Web Address (URL) of Paper | http://www.icassp2010.com/ |
Conference/Event | ICASSP 2010: 35th International Conference on Acoustics, Speech, and Signal Processing |
IEEE International Conference on Acoustics, Speech and Signal Processing | |
Event Details | ICASSP 2010: 35th International Conference on Acoustics, Speech, and Signal Processing Event Date 14 to end of 19 Mar 2010 Event Location Dallas, United States |
Event Details | IEEE International Conference on Acoustics, Speech and Signal Processing ICASSP |
Abstract | In this paper, a field-programmable gate array (FPGA) based enhanced architecture of the arithmetic coder is proposed, which processes two symbols per clock cycle as compared to the conventional architecture that processes only one symbol per clock. The input to the arithmetic coder is from the bit-plane coder, which generates more than two context-decision pairs per clock cycle. But due to the slow processing speed of the arithmetic coder, the overall encoding becomes slow. Hence, to overcome this bottleneck and speed up the process, a two-symbol architecture is proposed which not only doubles the throughput, but also can be operated at frequencies greater than 100 MHz. This architecture achieves a throughput of 210 Msymbols/sec and the critical path is at 9.457 ns. |
Keywords | arithmetic coding; EBCOT; FPGA; JPEG 2000; two-symbol architecture; clocks |
ANZSRC Field of Research 2020 | 400607. Signal processing |
461301. Coding, information theory and compression | |
400999. Electronics, sensors and digital hardware not elsewhere classified | |
Public Notes | Files associated with this item cannot be displayed due to copyright restrictions. |
Byline Affiliations | Department of Electrical, Electronic and Computer Engineering |
Beijing University of Posts and Telecommunications, China | |
Institution of Origin | University of Southern Queensland |
https://research.usq.edu.au/item/q06y9/an-fpga-based-fast-two-symbol-processing-architecture-for-jpeg-2000-arithmetic-coding
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